Non-volatile memory has evolved from the Electrically Erasable Programmable Read-Only Memory (EEPROM). An EEPROM is a type of non-volatile ROM that can be erased by exposing it to an electrical charge. The EEPROM provides programming on a per-byte basis. However, the density of the EEPROM is limited by its larger cell size. Flash memory was designed to have both a smaller cell size and a faster programming rate than EEPROM.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, flash drives, digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
A typical flash memory comprises a memory array organized in columns and rows. Changes in threshold voltage of the memory cells, through programming of charge storage structures (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase change or polarization), determine the data value of each cell. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed, such as by charging the charge storage structure. The data in a cell of this type is determined by the presence or absence of the charge in the charge storage structure. The charge can be removed from the charge storage structure by an erase operation.
Flash memory having a NOR architecture provides a smaller cell size and, thus, the possibility of greater memory density as compared to the EEPROM. A NOR architecture flash memory comprises a memory cell having a drain contact coupled to a data line (e.g., bit line) and a source contact coupled to a source line. The trade-off to obtaining the smaller memory cell size with the NOR architecture flash memory was that NOR architecture memory was no longer programmable on a byte basis. Erase of NOR architecture flash memory is on a block basis. Programming of NOR architecture is on a word, byte, or bit basis. NOR architecture also uses a logical—to—physical address table and wear leveling algorithm during programming.
A NAND architecture flash memory is organized as series strings of memory cells. Each series string of memory cells comprises a number of flash memory cells coupled serially drain-to-source between a select gate drain (SGD) transistor and a select gate source (SGS) transistor. One end of the series string is coupled to its respective bit line and the other end is coupled to a source line. The NAND architecture provides higher memory cell density than EEPROM as well as faster programming. However, the NAND architecture eliminated random reading of memory cells. Each read is performed on page basis.
For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for memory having the benefits of both EEPROM and flash memory.